1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection circuits, and in particular, to ESD protection circuits with reduced leakage currents.
2. Related Art
As is well known, integrated circuits have many semiconductor devices formed on semiconductor chips mounted in packages having multiple pins or electrodes. An ESD event at one or more of the pins of the package can cause a current flow through one or more of the semiconductor devices with such magnitude as to significantly damage or destroy the device. This is particularly true for more sensitive devices such as metal oxide semiconductor (MOS) devices which typically have thin gate oxides.
As is also well known, ESD circuits are often formed with and connected to vulnerable electrodes so as to absorb energy from an ESD event, thereby preventing damage or destruction of semiconductor devices connected such electrode.
A problem that often occurs with such ESD protection circuits, however, is that the introduction of such circuitry creates additional sources of or paths for leakage currents. Such leakage currents can reduce signal-to-noise ratios and dynamic signal operating ranges. This can be particularly true for complementary MOS (CMOS) operational amplifiers with their high input impedances and low input bias currents. With ESD protection diodes connected to the input devices, the resulting leakage reverse bias currents can vary significantly over temperature and semiconductor fabrication processes. This results in circuits having relatively large limits on the input bias current specifications.